WIOWIZ Technologies WIOWIZ EDA Platform
CONNECTED RTL VERIFICATION

The whole RTL Frontend flow, with WIOWIZ EDA Tools.

Point it at a design and every WIOWIZ engine connects into one flow: lint, clock-domain crossing, formal proofs, UVM simulation, power-aware analysis and low-power signoff. Full tool output streams live, and verdicts are exactly what the engines return.

One connected frontend flow

Each stage hands its design context and evidence to the next.

LNT
Lint
vWIZ-Lint
CDC
CDC / RDC
Truti
FV
Formal
proof apps
SIM
Simulation
FSiMX · UVM
PWR
Power-Aware
UPF
LP
Signoff
Vajra-LP

The engines behind the flow

FSX
FSiMXRTL, SDF, GLS and UVM simulation
CDC
TrutiCDC / RDC domain-crossing signoff
FV
Hetu-FormalProperty proofs and counterexamples
COV
AseshaFunctional and code coverage
WV
FSiMX-WaveWaveform debug, why, whyx and whydiff
LP
Vajra-LPLow-power and UPF verification
SOC
SoC VerifyParallel engines, one report
RVP
RVP BuilderGenerate and simulate a RISC-V SoC
AMS
WZ-SPICETransistor-level analog verification
WIOWIZ Platform │RTL Simulation │SystemVerilog │Lint: 276 rules │fsxrun: ready WIOWIZ Technologies
WIOWIZ EDA Platform
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Files
TERMINAL
Coverage ×

FSiMX Wave

Run a simulation with VCD dump enabled, then view waveforms here.

Individual tools

open any engine on its own

SoC Verify

Upload your SoC RTL - lint, CDC/RDC, simulation and power-aware lanes run in parallel. Every verdict links to the engine's raw, unfiltered log.

no files chosen (.sv/.v sources · optional .f filelist · optional .upf power intent)
Qualified bundled SoCs

Help & Support

Everything runs on our servers in your private workspace - nothing is installed on, or read from, your computer.

Getting started
New here? Take the 10-minute guided FSiMX example: run a simulation, read a failure, fix the RTL.
Open guided examples →
The terminal
Your workspace is a real Linux shell. Files persist between visits. fsxrun is on PATH; run any example with ./run.sh.
Open terminal →
Support & feedback
Found a bug, want a feature, or have a suggestion? Send it from here and a human engineer replies.
support@wiowiz.com
About
WIOWIZ - cloud EDA platform.
Engine: FSiMX (beta).
examples ●
▸ terminal - private workspace ~/examples ⟳ reconnect
Guided Labs ●
▸ lab terminal - private workspace ⟳ reconnect
Run a simulation to generate coverage analysis.
Coverage runs automatically when you run a simulation.
Truti - CDC / RDC Signoff
Structural clock- and reset-domain-crossing analysis. Upload your own RTL, or run a bundled design below.
no files selected
Bundled designs
Hetu-Formal - Property Proofs
Model-check safety invariants. PROVEN = holds for all reachable states; CEX = a counterexample trace was found.
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Bundled designs
Vajra-LP - UPF Power-Aware Signoff
Power intent (domains, isolation, retention) + a power-aware simulation that powers a domain down and back up.
Qualified examples
no files selected
vWIZ-SPICE - transistor-level AMS
Real SPICE (IHP SG13G2 BSIM3v3) on a WioWiz PHY. The solve runs server-side; only the eye, waveform and measurements come back, the netlist never leaves.
▸ADAS ChipFrontend verification flow · design source stays server-side
idle
pipeline_runner.sh - ready
Bus Architecture
CPU - Select One
IP Blocks - Click to Add
Configuration
WIOWIZ Platform │ RTL Simulation │ SystemVerilog │ Lint: 276 rules │ fsxrun: ... │ WIOWIZ Technologies